This application claims the priority benefit of Taiwan application serial no. 91106124, filed Mar. 28, 2002.
1. Field of Invention
The present invention relates to a read-only memory (ROM) and the fabrication thereof. More particularly, the present invention relates to an UV-programmed P-type mask read-only memory (Mask ROM) and the fabrication thereof.
2. Description of Related Art
In the prior art, a P-type Mask ROM usually comprises a lightly doped N-well in a substrate, a bit line in the N-well, a word line perpendicularly crossing over the bit line, an ONO composite layer between the N-well and the word line, and a silicon oxide layer between the bit line and the word line.
However, since the integration of electronic devices always gets higher and the dimensions of electronic devices become smaller and smaller correspondingly, a leakage current easily occurs between the bit lines during the operation of a P-type Mask ROM because of the small line-pitch. Accordingly, a method for fabricating a P-type Mask ROM is provided in the prior art to solve the leakage problem. The method features with performing a blanket erasing implantation after the bit lines and the word lines are formed, so as to increase the dopant concentration of the lightly doped N-well and thereby improve the leakage problem.
However, some problems are encountered in the modified process described above when the dosage of the blanket erasing implantation is poorly controlled. Specifically, when the dosage of the blanket erasing implantation is insufficient, the leakage problem still remains. When the dosage is too high, however, plenty of dopants will diffuse laterally into the channel to cause the Short Channel Effect (SCE).
Accordingly, this invention provides an UV-programmed P-type Mask ROM and a method for fabricating the same to prevent a leakage between the bit lines.
This invention provides a method for fabricating an UV-programmed P-type Mask ROM without a blanket erasing implantation. Therefore, the method can prevent the leakage problem or the short channel effect caused by an insufficient dosage or an excess dosage of the blanket erasing implantation in the modified P-type Mask ROM process in the prior art.
The method for fabricating an UV-programmed P-type Mask ROM of this invention is described below. At first, all memory cells are formed having raised threshold voltages to be in a first logic state (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d), in which the channel is hard to switch on. This can be done by, for example, forming a heavily doped N-well for the memory cells. A charge trapping layer is formed on the substrate comprising, for example, a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. Subsequently, a plurality of bit lines are formed in the heavily doped N-well and then an insulating layer, such as a thermal oxide layer, is formed on the bit lines. A conductive layer is formed on the substrate and then patterned into a plurality of word lines, wherein the substrate under a word line and between two bit lines serves as a memory cell. The patterning step is conducted by using the bottom oxide layer of the ONO layer as an etching termination layer, for example. An UV-blocking layer, such as an UV-absorbable layer, is formed over the substrate and then a plurality of openings are formed in the UV-blocking layer to expose selected memory cells that are predetermined to be in a second logic state (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d). An UV light is used to irradiate the substrate to inject electrons into the charge trapping layer under the openings to complete the programming process.
The UV-programmed P-type Mask ROM of this invention comprises a heavily doped N-well in a substrate, a plurality of bit lines in the heavily doped N-well, a plurality of word lines crossing over the bit lines, a charge trapping layer between the heavily doped N-well and the word lines, and an UV-blocking layer over the substrate. The UV-blocking layer is, for example, an UV-absorbable layer and has a plurality of openings over selected memory cells therein, and the selected memory cells are written by using UV light. The memory cells covered by the UV-blocking layer are in a first logic state (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) and the UV-written memory cells are in a second logic state (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d).
Since all memory cells are formed on a heavily doped N-well and then programmed by using UV light in this invention, the leakage current between the bit lines can be much reduced.
Moreover, since electrons can be trapped only in the nitride layer and the nitride layer not covered by the word lines is removed, the electrons can be confined in the ONO layer under the word lines not covered by the openings. Therefore, the threshold voltages of the selected memory cells can be lowered specifically and the short channel effect can be prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.